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STLC5460 line card interface controller board controller for up to 16 isdn lines or 16 voice subscribers. two serial interfaces : -pcm four bidirectional multiplexes -gci one (or two) at 2 mb/s. non blocking switch for 128 chan- nels (16, 32 or 64 kb/s bandwidth). n consecutive 64 kb/s channels from an input multiplex can be switched as a single n x 64 kbit/s channel to an output multiplex at 2048 kb/s. time slot assignment freely pro- grammable for every connected subscriber. programmable pcm data rates up to 8192 kb/s.constant data rate at 2 mb/s on gci side. pcm interface : - simple and double clock frequency selectable;. - programmable clock shift - tristate mode control signals for external drivers. gci interface : - six bits or four bits command/indicate channel selectable for analog or digital equipment - command/indicatemonitor channels validated or not microprocessor access to two selected bidirec- tional channels of gci and/or pcm. multicontrollers for layer 1 functions : - c/i protocol controller for up to 16 c/i channels - monitor protocol controller for up to 16 monitor channels. standard microprocessor interface with multi- plexed address/data bus or separate address data buses. plcc44 pins package february 1997 1 2 3 5 64 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 34 35 33 32 31 30 29 40 41 42 44 43 23 22 21 19 18 20 28 27 26 24 25 vdd1 a0 rdd3 rxd1 rxd0 rxd2 dout1 dout0 p0 res nrdy/nwait a1 tsc0 txd0 tsc1 tsc2 txd1 txd2 tsc3 txd3 pfs pdc a3 din0 din1 vss2 fsc vdd2 dcl int ale/as ncs rw/nwr ad4 ad3 ad2 ad0 a2 ad1 ds/nrd v ss ad7 ad5 ad6 d94tl149b pin connection (top view) plcc44 ordering number: STLC5460 1/54
description the line card interface controller, STLC5460, is a monolithic switching device for the path control of up to 128 channels of 16, 32, 64 kbps band- width. two consecutive 64 kbps channels may also be handled as a quasi single 128 kbps chan- nel. for these channels, the lcic performs non- blocking space time switching between two serial interfaces: the system interface (or pcm inter- face) and the general component interface (gci). pcm interface can be programmed to operate at different data rates between 2048 and 8192 kbps. the pcm interface consists of up to four duplex ports with a tristate indication signal for each out- put line. the gci interface can be selected to be pcm interface at 2mbit/s. the lcic can be programmed to communicate with gci compatible devices such as stlc3040 (slic), stlc5411 (u interface) and others. the device manages the layer 1 protocol buffering the command/indicate and monitor channels for gci compatible devices. due to its capability to switch channels of different bandwidths, the STLC5460 can handle up to 16 isdn subscribers with their 2b+d channel struc- ture in gci configuration, or up to 16 analog sub- scribers. since its interfaces can operate at differ- ent data rates, the lcic is an ideal device for data rate adaptation between pcm interface up to 8mb/s and gci at 2mb/s. the device gives the possibility of checking the correct communication inside the pbx or public central office providing : - independentpcm delay setting - pcm comparison function - pseudo randomsequencegeneratorand analyser. moreover, the lcic is one of the key building blocks for networks with either central, distributed or mixed signaling and packet data handling ar- chitectures associated with st5451 (hdlc con- troller). the device is controlled by a standard 8 bit paral- lel microprocessor interface with a multiplexed address-data bus. the device may optionally be controlled by separate address and data buses. destination reg command reg source register command memory 194 words of 14 bits counters parallel serial shifting 4 pcm 2 gci c/i, mon transmit 16 indipendent controllers special switch at 16, 32, 64 kb/s extraction 2x 64 kbit channel (address) (data) (data) switching memory 194 bytes (4pcm+2gci + 2 channel -insertion- = 128+64+2=194) counters c/i, mon receiver insertion 2x64 kbit channel serial parallel shifting 4 pcm 2 gci 1 bit for 16 tristate 6 bits d94tl160a block diagram STLC5460 2/54
pin definitions and functions symbol pin number type (*) function vdd1 1 i supply voltage 5v, 5% . a0 2 i (**) non multiplexed mode: this input interfaces to the system's address bus to select an internal register for a read or write access. multiplexed mode: a0 at vdd, nrdy/nwait pin delivers nwait a0 at vss, nrdy/nwait pin delivers nready rxd3 rxd2 rxd1 rxd0 3 4 5 6 i receive pcm interface data : serial data is received at these lines at standard ttl or cmos levels. a1 7 i (**) non multiplexed mode: this input interfaces to the system's address bus to select an internal register for a read or write access. multiplexed mode: a1 at vdd, ncs signal provided by the system is not inverted by the circuit. a1 at vss, ncs signal provided by the system is inverted by the circuit. tsc0 tsc1 tsc2 tsc3 8 10 12 14 od tristate control for the pcm interface. these lines are low when the corresponding txd outputs are valid. txd0 txd1 txd2 txd3 9 11 13 15 o transmit pcm interface data : serial data is sent by these lines at standard ttl or cmos levels. these pins can be tristated. pfs 16 i pcm interface frame synchronization pulse. pdc 17 i pcm interface data clock, single or double rate. a2 18 i (**) non multiplexed mode: this input interfaces to the system's address bus to select an intenal register for a read or write access. multiplexed mode: a2 at vdd, as/ale signal providedby the system is not inverted by the circuit a2 at vss, as/ale signal provided by the system is inverted by the circuit ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 19 20 21 22 23 24 25 26 i/o address data bus. if the multiplexed address/data m p interface bus mode is selected these pins transfer data and commands between the m p and the STLC5460. if a demultiplexed mode is used, these bits interface with the system data bus. vss1 27 i ground : 0v ds/nrd 28 i motorola like mode: data strobe intel like mode: not read the signal indicates a read operation, active low rw/nwr 29 i motorola like mode: read/write intel like mode: not write the signal indicates a write operation, active low. ncs 30 i not chip select. a low on this line selects the STLC5460 for a read/write operation. (*): (i) input (o) output (io) in/output (od) open drain (**): with pull up resistance. STLC5460 3/54
pin definitions and functions (continued) symbol pin n plcc type function as/ale 31 i multiplexed a/d mode: used to latch the address from adn non multiplexed a/d mode: this pin at vss indicates intel like interfaces this pin at vdd indicates motorola like interfaces. int 32 od interrupt line, active low. dcl 33 0 data clock output. fsc 34 o frame synchronization output. vdd2 35 i power supply : 5v vss2 36 i ground. din1 37 i gci data input 1 din0 38 i gci data input 0 a3 39 i (**) non multiplexed mode: this input interfaces to the system's address bus to select an internal register for a read or write access. multiplexed mode: a3 at vdd, ds/nrd signal provided by the system is not inverted by the circuit a3 at vss, ds/nrd signal provided by the system isinverted by the circuit dout0 40 o gci data output 0 dout1 41 o gci data output 1 po 42 i (**) p0 at vss: variable access mode p0 at vdd: fixed access mode nrdy/n wait 43 od if p0 at vss: intel like mode: this pin delivers nrdy motorola mode: this pin delivers nwait res 44 i reset. a logical high on this input forces the STLC5460 into the reset state (*): (i) input (o) output (io) in/output (od) open drain (**): with pull up resistance. dcl fsc dout0 din0 dout1 din1 mux0/gci0 mux1/gci1 lcic pcm3 pcm0 pcm1 pcm2 pdc pfs rxd3 txd3 tsc3 rxd0 txd0 tsc0 rxd1 txd1 tsc1 rxd2 txd2 tsc2 microprocessor interface d94tl159a clocks figure 1: gci and pcm interfaces. STLC5460 4/54
line card applications the lcic is designed to fit both digital and ana- logue line card architectures. it supports up to 16 isdn subscribers or 16 voice subscribers. the level 1 devices are connected to st5451 circuits to perform the d channel han- dling. analogue line card in analogue line cards lcic controls signalling, voice and data path of 64 kb/s channels. when used in combination with l3040/l300 0n, it allows to implement an optimised line card archi- tecture: the lcic controls the configuration of l3040 and exchange signalling with the l3040. digital line card in digital line cards lcic controls the configura- tion of level 1 circuits (u or s interface) by means of mon channel configuration and per- forms activation/deactivation by means of com- mand/indicate protocol. lcic switches the b channels and can switch the d channels if the processing is centralised. functional description pcm interface the pcm interface registers configure the data transmitted or received at the pcm port, for one pcm, the maximum data rate can change de- pending on the mode selected: pcm mode 0: max rate 2048 kb/s with four pcm ports active pcm mode 1: max rate 4096 kb/s with two pcm ports active pcm mode 2: max rate 8192 kb/s with one pcm ports active. the oactual datao rate may be varied in a wide range without programming. an automate computes the number of clock per frame. hence, the data rate can be stepped in 8, 16 or 32 kb/s in increments in pcm mode 0, 1, 2 respectively. the clock frequency of pdc is equal to once or twice the data rate, see fig 1 and 2. when operat- ing at single rate (2048 kb/s) and not at double clock frequency (4096 khz), an onchip clock fre- quency doubler provides a 4098 khz clock for the gci interface (dcl). the rising edge of pfs signal is used to deter- mine the first bit of the first time slot of the frame. the length of pfs pulse is one bit-time at least and the length between two pulses can be also one bit time. after reset, the lcic reaches synchronism having received two consecutive correct pfs pulses. synchronisation is considered lost by the device if the pfs signal is not repeated with the correct repetition rate which has been stored by the cir- cuit at the beginning of synchronisation research. the lsync bit in the interrupt register indicates if the component is synchronised or not: a logical 0 indicates the synchronous state, a logical o1o shows that the synchronism has been lost. the relation between the framing signal pfs and the bit stream is controlled by the contents of ipof, opof and cpof registers. these regis- ters denote the number of bit times the pcm frame is shifted. each pcm multiplex can be pro- grammed with different shifts . without programming the bit shift function of the pcm interface, the rising edge of the pfs signal marks the first bit of input pcm frame and the first bit of output pcm frame. see fig 3 gci interface the monitor and the command/indicate channels may be validated or not, in this second case the b3 and b4 channels become standard channels at 64 kb/s. when validated command/indicate channel may be configured with four bits for digital cards or six bits for analogue cards. the clocks (bit clock and frame clock) are deliv- ered by the device with double rate clocking or simple rate clocking. fsc and dcl are output signals derived from pfs and pdc which are input signals. gci pcm dcl clock khz data kb/s pdc clock (khz) data rate kb/s mode simple (*) double simple double 2.048 4.096 2.048 2.048 2.048 mode 0 2.048 4.096 2.048 4.096 2.048 mode 0 2.048 4.096 2.048 4.096 4.096 mode 1 2.048 4.096 2.048 8.192 4.096 mode 1 2.048 4.096 2.048 8.192 8.192 mode 2 2.048 4.096 2.048 16.384 8.192 mode 2 (*) as gci format but with simple clock. STLC5460 5/54
first bit of the frame first bit of the frame first bit of the frame first bit of the frame del=1 dcl=1 pfsp=1 del=0 dcl=1 dcl=1 pfsp=0 del=0 dcl=1 mode not delayed: del=1 pfs pfs pfs pfs pdc pdc pdc pdc pfsp=0 pfsp=1 mode delayed: clocks received by the circuit figure 1: pcm interface. alignment in double clock mode. STLC5460 6/54
first bit of the frame first bit of the frame del=0 dcl=1 del=0 dcl=0 mode not delayed pfsp=0 pfsp=1 del=1 dcl=1 dcl=1 mode delayed del=1 pfsp=0 pfsp=1 pfs pdc pfs pdc pfs pdc pfs pdc first bit of the frame first bit of the frame clocks received by the circuit figure 2: pcm interface. alignment in simple clock mode. STLC5460 7/54
double clock dcp =1 pdc dout dout din din odl=0 gci like odl=1 ispp=0 gci like ispp=1 pdc dout dout din odl=0 odl=1 simple clock dcp=0 figure 3: pcm interface. clock and data in/data out. STLC5460 8/54
memory structure and switching the lcic contains three memories: auxiliary memory (am), data memory (dm) and control memory (cm). the auxiliary memory consists of one block di- vided in four parts of 16 words. this auxiliary memory is used for validated data from monitor and command/indicate rx channels and to transmit data to monitor and com- mand/indicate tx channels. the data memory buffers the data input from the pcm and the gci interface. it has a capacity of 128 + 64 time slots to buffer 4 pcm frame of 32 time slots and two gci interfaces. it is written pe- riodically once every 125 microseconds controlled by the input counters associated to pcm interface and to gci interface. to perform the switching the loopback function, this memory is read, random, in accordance with the control memory the control memory has a capacity of 128 + 64 words of 14 bits: 8 of data and 6 of code. the 14 bits are written random, via microprocessor in- terface and read cyclically under the control of the output counters associated to pcm interface and gci interface. for control memory access and different func- tions, three registers are provided: destination register: it contains the address of a specific location of the control memory; source register : it contains the data (to be written or read) of the control memory corrisponding to the address indi- cated by the destination register; command register: it contains the code (6 bits to be written or read) of the control memory. the content of command register defines the dif- ferent capabilities: switching at 64 kb/s, 32 kb/s, 16 kb/s, loopback and also extraction/insertion from the microprocessor interface. a memory access using the actual command reg- ister and source register is performed upon every destination register write access. the processing of the memory access takes at most 488ns. microprocessor interface after reset, the microprocessor interface is in non-multiplexed mode (address bus and data bus must be non-multiplexed): if ale pin is hardwired at vss, the microproces- sor interface is motorola like, address/data are non-multiplexed. if ale pin is hardwired at vdd the microproces- sor interface is intel like, address/data are non- multiplexed. after reset, as soon as two successive edges are detected on ale pin (rising and falling edges) by the circuit the microprocessor interface switches in multiplexed mode (address bus and data bus must be multiplexed). the circuit is set automat- ically in motorola like or in intel like mode. for the circuit address bus and data bus multi- plexed or not multiplexed, the difference between motorola like and intel like mode is showed in fig. 4. figure 4. STLC5460 9/54
the microprocessor interface type is set via p0 pin as shown hereafter : p1 is an outputand it is not used if p0 = 1. the device selects automatically either motorola interface or intel interface. p0 p1 automatical selection 1 z intel mux mode motorola mux mode intel demux mode motorola demux mode 0 if a0 = 1 p1 pin delivers wait automatically if a0 = 0 p1 pin delivers ready automatically moreover, for a multiplexed mode m p interface, a1 to a3 pins mean : a1 = 1: cs signal provided by the system is not inverted by the device a1 = 0: cs signal provided by the system is in- verted by the device a2 = 1: as signal provided by the system is not inverted by the device a2 = 0: as signal provided by the system is in- verted by the device a3 = 1: ds signal provided by the system is not inverted by the device a3 = 0: ds signal provided by the system is in- verted by the device. c/i and mon channels, extra channels the command/indicate and monitor channels can be validated or not: if validated, the c/i and mon protocol controllers operate and it is not possible to use this channels for switching, if not validated the protocols are in- hibited and the channels can be used as ex- trachannels for switching. command/indicate protocol sixteen c/i channels are implemented, one bit of the configuration register mconf1, indicates the number of bits of the primitive (four or six bits) for all the channels. to transmit a primitive into one of the 16 chan- nels, the mp loads the primitive (4 or 6 bits) into source register and the number of the c/i chan- nel into destination register with w/r bit of com- mand register at o0o. the two more significant bits of the source regis- ter indicates if the primitive, bit0/5 of the same register, has not been transmitted yet, transmitted once, twice or more . when a new primitive has been received twice identical, on one of the 16 c/i channels, an inter- rupt is generated, the number of the c/i channel (4 bits) is written in the receive c/i status regis- ter , and the primitive received is in the auxiliary memory, all accessible to the m p moreover, the microprocessor can read directly the 16 primitives that have been received and stored into the receive c/i memory. to read this memory the m p load in the source register the number of receive c/i channel it wants, and in the destination register reads the primitive (4 or 6 bits) with a seventh bit which indicates whether the primitive has been received once or twice identical. vedi figura read aux mem receive c/i channels. monitor channel protocol sixteen monitor channels are implemented. to transmit a message the m p load into destination register with w/r bit of command register at 1 the number of mon channels, and into source register the message; this byte is transmitted if byte bit of command register is at 1. this procedure is repeated for each byte of the message if it is longer than one byte. when a new byte has been received twice identi- cal from one of the sixteen monitor channels an interrupt is generated, the number of mon channel (4 bits) is written in receive monitor status register and the last byte received is writ- ten in receive data monitor channel memory. the remote transmitter will transmit the next byte after reading of this register by the local micro- processor. insertion - extraction this function allows to insert data into gci and pcm channels and to extract data from gci and pcm interface. these data are provided either by the microprocessor or by an internal pseudo ran- dom sequence generator. insertion two programmable registers (insert a and b) contain the data to insert into two output time slots continuously. to perform an insertion, four registers are programmed by the microprocessor: - in the insert a and/or b registers it writes the data to insert. - in the source registers it writes the a and/or b register address - in the destination register it writes the output interface, pcm or gci, and the time slot se- lected. STLC5460 10/54
- in the command register it writes the indica- tion if insert into 64 kb/s, 32 kb/s or 16 kb/s channel. when the data has been inserted, status bit (ins) of status register is put at logical 1 and an interrupt is generated. extraction two programmable registers (extract a and b) contain the data extracted from two input time slots. to perform an extraction, three registers are processed by the microprocessor : - extract a and/or b registers to read the data extracted. - the source register to indicate the input inter- face, pcm or gci, and the time slot se- lected. when the data is loaded in extract a or ex- tract b register, the bit ext of status reg- ister is put at logical 1,and an interrupt is gen- erated. list of register name mux mode read only demux mode ad5 to ad1 (h) rbs a3 to a0 rbs iir comp mconf1 mconf2 pconf cpof ipof opof ipsh1 ipsh2 opsh1 opsh2 ipass opass imass omass status ecr cmr src dst insa insb exta extb int mask rmos tmos rcis test 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 (00) (01) (02) (03) (04) (05) (06) (07) (08) (09) (0a) (0b) (0c) (0d) (0e) (0f) (11) (12) (13) (14) (15) (16) (17) (18) (19) (1a) (1b) (1c) (1d) (1e) (1f) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x r r r r r r r 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 nb in mux mode ad7, ad6, ad0 and rds bits are ignored STLC5460 11/54
configuration register description initialisation and identification register (iir) 7 0 rbs rst t1 t0 v3 v2 v1 v0 after reset 3f (h) t1/t0 test functions t1 t0 description 0 0 normal state 0 1 command memory or auxiliary auto reset. if cm = 1 (bit of command register): the six lower bits of command register and the eight bits of source register are stored into each address of command memory. if cm = 0 (bit of command register) : the eight bits of source register are stored into each address of monitor auxililary memory and the six lower bits of source register are stored intocommand/indicate auxilliary memory. the 16 c/i and monitor channels are ready to transmit and to receive data.after autoreset, busy and t0 goes to o0o. 1 1 auto test. this function is reserved for manufacturer. - the pseudo random sequence generator is connected instead of insert a register and pseudo random sequence analyzer is connected instead of extract a register. - the command memory is loaded thanks to a special algorithm in order to switch the sequence provided by the generator into tso of pcmo, then the contents of tso of pcmo into ts1 of pcmo, then the contents of ts1 of pcmo into ts2 of pcmo and so on. finally, the contents of ts31 of mux1 are taken into account by the pseudo random sequence analyzer.after loading command memory, 193 switching are set up in real time.the analyzer receives the pseudo random sequence from the generator after switching. if lp = 1, the loopback is internal. if lp = 0, an external loopback must be performed. so, command memory and data memory can be checked in the same time. 1 1 reserved. initialise cm so that the content of each input time slot t of input multiplex m is switched to output time slot t of output multiplex m rbs register bank selection. rbs = 0. the 16 first main registers are selected (0 to 15). rst reset soft. the programmable registers are reset. v3/v0 these bits are fixed at 0 comparison register (comp) 7 0 newe tim cp6 cp5 cp4 cp3 cp2 cp1 after reset 00 (h) newe new extract. when newe = 1, ext interrupt is generated only if a new word is loaded into extract registers (a or b). tim timer, associated to ins of int register and to timo/1 of cpof register. tim = 1 tim0/1 bits of cpof register are taken into account tim = 0 an interrupt is generated each 125 m s. STLC5460 12/54
cp 6/1 comparison 6 to 1. bit stream of one pcm and bit stream of another pcm are compared at each bit time, if there is difference, pdif interrupt is generated. comparison between cp1 = 1 pcm0 and pcm1 cp2 = 1 pcm1 and pcm2 cp3 = 1 pcm2 and pcm3 cp4 = 1 pcm0 and pcm2 cp5 = 1 pcm1 and pcm3 cp6 = 1 pcm0 and pcm3 multiplex configuration 1 register (mconf1) 7 0 cim mom ci4mi ci4m0 - - gcim1 gcim0 after reset 3f (h) cim command/indicate mode. cim = 1: the controller ignores the new received primitive if the previous has not been read by the microprocessor. cim = 0: the controller overwrites the previous primitive without condition when it receives a new primitive. mom monitor channel mode mom = 1: if bytes are not received twice identical the message is aborted. mom = 0: if bytes are not received twice identical the mom controller doesn't acknowledge the received byte (gci standard). ci4m1 command indicate 4 bits for multiplex 1. ci4m1 = 0: command indicate primitive has six bits. ci4m1 = 1: command indicate primitive has four bits. ci4m0 command indicate 4 bits for multiplex 0. ci4m0 = 0: command indicate primitive has six bits. ci4m0 = 1: command indicate primitive has four bits. gcim1 gci multiplex 1. gcim1 = 1: the multiplex m1 is gci, it includes eight gci channels. gcim1 = 0: the multiplex m1 includes 32 time slots. (pcm like channel) gcim0 gci multiplex 0. gcim0 = 1: the multiplex m0 is gci, it includes eight gci channels. gcim0 = 0: the multiplex m0 includes 32 time slots. (pcm like channel) multiplex configuration 2 register (mconf2) 7 0 - - m1d m0d ispm timd mod dckm after reset ff (h) m1d multiplex 1 disable. m1d = 1. multiplex 1 output is at high impedance continuously, multiplex 1 input is forced to o1o, if it is gci. STLC5460 13/54
m0d multiplex 0 disable. m0d = 1. multiplex 0 output is at high impedance continuously, multiplex 0 input is forced to o1o, if it is gci. timd timer monitor channel disabled. timd = 1. the timer 1ms is disabled for each transmit monitor channel. ispm input sampling multiplex. ispm = 0. the input bit is sampled at half bit time. ispm = 1. the input bit is sampled at 3/4 bit time. mod multiplex open drain. mod = 1. the two multiplex outputs are open drain. mod = 0. the two multiplex outputs are at low impedance dckm double clock for multiplex. dckm = 1. dcl is twice data rate (ex : if data rate = 2048 kb/s,dcl = 4096 khz). dckm = 0. dcl is simple clock. pcm configuration register (pconf) 7 0 0 tsnb del pfsp odl ispp pod sckp after reset 00 (h) tsnb time slot numbering. tsnb defines the order of ts on the pcm when the data rate is 4 mb/s or 8 mb/s related to the order of ts on the pcm at 2 mb/s (see table hereafter). del delayed mode for each pcm. del = 1. a delay of one clock pulse is applied to the first bit of the frame of each pcm. del = 0. pfs indicates the first bit of the frame for each pcm (if offset and shift are zero). pfsp pcm frame synchronisation sampling. pfsp = 0. pfs signal is sampled on the fall edge of pdc signal. pfsp = 1. pfs signal is sampled on the rise edge of pdc signal. odl output delay. odl = 0. the bits are shifted out with zero delay. odl = 1. the bits are shifted out with a delay of one half bit time. ispp input sampling pcm. ispp = 0. the input bit is sampled at half bit time. ispp = 1. the input bit is sampled at 3/4 bit time. pod pcm open drain. pod = 1. the pcm outputs are open drain pod = 0. the pcm outputs are at low impedance. sckp simple clock for pcm. sckp = 0. pdc signal is twice data rate. (ex : if data rate = 2048 kb/s, pdc = 4096 khz). sckp = 1. pdc is simple clock STLC5460 14/54
ts and pcmn at 4 mb/s with n = 0 or 2 ts0 ts1 ts2 ts3 ts30 ts31 ts32 ts62 ts63 tsnb = 1 ts at 2mb/s ts0 ts0 ts1 ts1 ts15 ts15 ts16 ts31 ts31 pcm at 2mb/s pcmn pcmn+1 pcmn pcmn+1 pcmn pcmn+1 pcmn pcmn pcmn+1 tsnb = 0 ts at 2mb/s ts0 ts1 ts2 ts3 ts30 ts31 ts0 ts30 ts31 pcm at 2mb/s pcmn pcmn+1 ts and pcm0 at 8 mb/s ts0 ts1 ts2 ts3 ts4 ts124 ts32 ts62 ts63 tsnb = 1 ts at 2mb/s ts0 ts0 ts0 ts0 ts1 ts31 ts31 ts31 ts31 pcm at 2mb/s pcm0 pcm1 pcm2 pcm3 pcm0 pcm0 pcm1 pcm2 pcm3 ts and pcm at 8mb/s ts0 to ts31 ts32 to ts63 ts64 to ts95 ts96 to ts127 tsnb = 0 ts at 2mb/s ts0 to ts31 ts0 to ts31 ts0 to ts31 ts0 to ts31 pcm at 2mb/s pcm0 pcm1 pcm2 pcm3 complementary pcm offset register (cpof) 7 0 pmd1 pmd0 tim1 tim0 oof1 iof0 iof1 iof0 after reset 00 (h) pmd1/0 pcm mode pmd1 pmd0 the pcm are at 0 0 2048 kbit/s 0 1 4096 kbit/s 1 0 8192 kbit/s 1 1 not used. tim 1/0 these bits are taken into account only if bit tim of comp register is at 1; in this case an inter- rupt is generated periodically and tim 1/0 defines the period tim1 tim0 period 0 0 1ms 0 1 8ms 1 0 64ms 1 1 250ms oof1/0 output offset 1/0. these two bits are associated with oof2/9 ofopof register. iof1/0 input offset 1/0. these two bits are associated with iof2/9 of ipof register. STLC5460 15/54
input pcm offset register (ipof) 7 0 iof9 iof8 iof7 iof6 iof5 iof4 iof3 iof2 after reset 00 (h) iof9/2 input pcm offset 9 to 2. associated with iof1/0, these ten bits indicate the delay between pfs signal and the first bit of the frame, for each input output pcm offset register (opof) 7 0 oof9 oof8 oof7 oof6 iof5 oof4 oof3 oof2 after reset 00 (h) oof9/2 output pcm offset 9 to 2. associated with oof1/0 of complementary offset register, these ten bits indicate the delay between bit 0 of the frame out going versus bit 0 of the frame incoming. input pcm shift 1 (ipsh1) 7 0 0 p1sh2 p1sh1 p1sh0 0 p0sh2 p0sh1 p0sh0 after reset 00 (h) p1sh2/0 pcm1 shift 2 to 0. this number (0 to 7) is added to input pcm offset to obtain the total shift of the frame of pcm1. p0sh2/0 pcm0 shift 2 to 0. this number (0 to 7) is added to input pcm offset to obtain the total shift of the frame of pcm0. input pcm shift 2 (ipsh2) 7 0 0 p3sh2 p3sh1 p3sh0 0 p2sh2 p2sh1 p2sh0 after reset 00 (h) p3sh2/0 pcm3 shift 2 to 0. this number (0 to 7) is added to input pcm offset to obtain the total shift of the frame of pcm3. p2sh2/0 pcm2 shift 2 to 0. this number (0 to 7) is added to input pcm offset to obtain the total shift of the frame of pcm2. output pcm shift 1 (opsh1) 7 0 p1e p1sh2 p1sh1 p1sh0 p0e p0sh2 p0sh1 p0sh0 after reset 00 (h) p1e output pcm1 enable. p1e = 0. pcm1 output is at high impedance. p1e = 1. pcm1 output is enable. STLC5460 16/54
p1sh2/0 pcm1 shift 2/0. this number (0 to 7) is added to output pcm offset to obtain the total shift of the frame of pcm1. p0e output pcm2 enable. p0e = 0. pcm0 output is at high impedance. p0e = 1. pcm0 output is enabled. p0sh2/0 pcm0 shift 2/0. this number (0 to 7) is added to output pcm offset to obtain the total shiftof the frame of pcm0. output pcm shift 2 (opsh2) 7 0 p3e p3sh2 p3sh1 p3sh0 p2e p2sh2 p2sh1 p2sh0 after reset 00 (h) p3e output pcm3 enable. p3e = 0. pmc3 output is at high impedance. p3e = 1. pcm3 output is enabled. p3sh2/0 pcm3 shift 2/0. this number (0 to 7) is added to output pcm offset to obtain the total shiftof the frame of pcm3. p2e output pcm2 enable. p2e = 0. pcm2 output is at high impedance. p2e = 1. pcm2 output is enabled. p2sh2/0 pcm2 shift 2/0. this number (0 to 7) is addedto outputpcm offsetto obtain the totalshift ofthe frame of pcm2 input pcm assignment register (ipass) 7 0 ip31 ip30 ip21 1p20 1p11 1p10 1p01 1p00 after reset e4 (h) ip31/ip30 incoming pcm3 assignment. ip31 ip30 incoming pcm3 receives data from 0 0 1 1 0 1 0 1 pin rxd0 pin rxd1 pin rxd2 pin rxd3 (default value) ip21/ip20 incoming pcm2 assignment. ip21 ip20 incoming pcm2 receives data from 0 0 1 1 0 1 0 1 pin rxd0 pin rxd1 pin rxd2 (default value) pin rxd3 ip11/ip10 incoming pcm1 assignment. ip11 ip10 incoming pcm1 receives data from 0 0 1 1 0 1 0 1 pin rxd0 pin rxd1(default value) pin rxd2 pin rxd3 STLC5460 17/54
ip01/ip00 incoming pcm0 assignment. ip01 ip00 incoming pcm2 receives data from 0 0 1 1 0 1 0 1 pin rxd0(default value) pin rxd1 pin rxd2 pin rxd3 output pin assignment register (opass) 7 0 op31 op30 op21 op20 op11 op10 op01 op00 after reset e4 (h) op31/op30 output pin 3 assignment. op31 op30 pin txd3 receives data from 0 0 1 1 0 1 0 1 outgoing pcm0 outgoing pcm1 outgoing pcm2 outgoing pcm3 (default value) op21/op20 output pin 2 assignment. op31 op30 pin txd2 receives data from 0 0 1 1 0 1 0 1 outgoing pcm0 outgoing pcm1 outgoing pcm2 (default value) outgoing pcm3 op11/op10 output pin 1 assignment. op11 op10 pin txd1 receives data from 0 0 1 1 0 1 0 1 outgoing pcm0 outgoing pcm1 (default value) outgoing pcm2 outgoing pcm3 op01/op00 output pin 0 assignment. op01 op00 pin txd0 receives data from 0 0 1 1 0 1 0 1 outgoing pcm0 (default value) outgoing pcm1 outgoing pcm2 outgoing pcm3 input multiplex assignment register (imass) 7 0 - - - - 0im10im0 after reset 04 (h) im1 incoming multiplex 1 assignment. im1 incoming multiplex 1 receives data from 0 1 pin din 0 pin din 1 (default value) STLC5460 18/54
im0 incoming multiplex 0 assignment. im0 incoming multiplex 0 receives data from 0 1 pin din 0 (default value) pin din 1 output multiplex assignment register (omass) 7 0 - - - - 0 do1 0 do0 after reset 04 (h) do1 output 1 pin assignment. do1 dout 1 pin receives data from 0 1 outgoing multiplex 0 outgoing multiplex 1 (default value) do0 output 0 pin assignment. do1 dout 0 pin receives data from 0 1 outgoing multiplex 0 (default value) outgoing multiplex 1 working register description command register (cmr) 7 0 r/w cm cr5 cr4 cr3 cr2 cr1 cr0 after reset 00 (h) r/w read/write r/w = 0. write memory. address bits are provided by the destination register (dst) data bits are provided by the source register (src) r/w = 1. read memory. address bits are provided by the destination register (dst) data bits will be in source register (src) when busy (status register) will go to o0o. cm command memory. cm = 1 access to command memory cm = 0 access to auxiliary memory. cr 5/0 the meaning of these bits depends on the value of cm and r/w. the description is given thereafter. cm = 1 command memory cm = 0 auxiliary memory command register bit 5 to 0 subchannel configuration command if write memory status if read memory source register 1 of 192 input time slots or 1 of 2 insertion registers byte if mon channel or primitive if c/i channel. destination register 1 of 192 output time slots or 1 of 2 extraction registers 1 of 16 mon channels or 1 of 16 c/i channels following you will find a detailed explanation case by case of the meaning of all the bits of this register. STLC5460 19/54
first case cm = 1: access to command memory cm cr5 cr4 cr3 cr2 cr1 cr0 r/w 1 ch1 ch0 ss1 ss0 ds1 ds0 after reset 00 (h) r/w read/write r/w = 0 (write). the eight bits of source register and the six lower bits of this command register are loaded into the command memory (14 bits). the address bits are given by the destination register (8 bits). write cycle starts when destination register is loaded by the microprocessor. r/w = 1 (read). the 14 bits of command memory addressed by the destination register are loaded respectively into command register (6 bits) and source register (8 bits). read cycle starts when destination register is loaded by the micro-processor. ch0/1 channel data rate ch1 ch0 description 00 the output is at high impedance during the time slot selected 01 16kb/s subchannel is selected 10 32kb/s subchannel is selected 11 64kb/s channel is selected during the time slot selected, the output is at high impedance for the subchannelsnot selected. ss 0/1 source subchannel selected. data rate ss1 ss0 source channel 16kb/s 0 0 bits 6-7 0 1 bits 4-5 1 0 bits 2-3 1 1 bits 0-1 32kb/s 0 0 bits 4 to 5 0 1 bits 0 to 3 bit 7 is trasmitted first. ds 0/1 destination subchannel selected. data rate ss1 ss0 source channel 16kb/s 0 0 bits 6-7 0 1 bits 4-5 1 0 bits 2-3 1 1 bits 0-1 32kb/s 0 0 bits 4 to 5 0 1 bits 0 to 3 bit 7 is trasmitted first. STLC5460 20/54
second case cm = 0: access to auxiliary memory microprocessor writes auxiliary memory to transmit primitives for each tx c/i channel and to transmit bytes of message for each tx mon channel. microprocessor reads auxiliary memory to recover primitive received by each rx c/i channel and to re- cover the message received by each rx mon channel. tx command indicate channel - selected by destination register (dst) cm cr5 cr4 cr3 cr2 cr1 cr0 r/w 0 - - - - pt1 pt0 r/w = 1 read auxiliary memory after writing this register with r/w=1 and when busy(status register) has gone to 0, the bits of the register have the following meaning: cr5/cr2 not used pt0/1 primitive trasmitted pt1 pt0 status 00 primitive has not been transmitted yet 01 primitive has been transmitted once 10 primitive has been transmitted twice 11 primitive has been transmitted more than twice. r/w = 0 write auxiliary memory. cr0/cr5 not used rx command indicate channel - selected by destination register (dst) cm cr5 cr4 cr3 cr2 cr1 cr0 r/w 0 - - - - ovr pr r/w = 1 read auxiliary memory after writing this register with r/w=1 and when busy(status register) has gone to 0, the bits of the register have the following meaning: cr5/cr2 not used ovr overrun ovr = 1. the previous primitive has not been read by the microprocessor. pr primitive received. pr = 1. the primitive has been received once pr = 0. the primitive has been received twice or more. the primitive is in source register. r/w = 0 writing auxiliary memory. cr0/cr5 not used STLC5460 21/54
tx monitor channel selected by destination register. r/w cm cr5 cr4 cr3 cr2 cr1 cr0 0 0 - - - last byte init ir/w = 0 writing auxiliary memory. cr5/cr3 not used last last byte. this bit is associated with byte. if last = 1, last byte of the message. if last = 0, current byte byte byte to transmit. init when this bit is at 1, the mon channel defined in src register is initialised and the monitor channel is idle (all o1os are transmitted) r/w cm cr5 cr4 cr3 cr2 cr1 cr0 1 0 - t0 abt last byte idle r/w = 1 read auxiliary memory after writing this register with r/w=1 and when busy(status register) has gone to 0, the bits of the register have the following meaning: to time out = one millisecond. this bit goes to 1 when the remote receiver has not acknowledged the byte after 1 millisecond. abt abort. abt = 1 the remote receiver has aborted the message transmitting. last last byte. this bit is associated with byte. if last = 1, last byte of the message. if last = 0, current byte. byte byte = 1 byte transmitting. byte = 0 byte transmitted and acknowledged by the remote receiver, a new byte can be transmitted. idle idle = 1 monitor channel, a bit, e bit are at o1o. rx monitor channel- selected by destination register cm cr5 cr4 cr3 cr2 cr1 cr0 r/w 0 - - - ab byte eom r/w = 1 read auxiliary memory after writing this register with r/w=1 and when busy(status register) has gone to 0, the bits of the register have the following meaning: ab abort. ab = 1 the receiver has detected an error during the transmission. STLC5460 22/54
byte new byte. byte = 1 a new byte is available in the source register eom end of message eom = 1 : there is no significant byte in the source register. the previous byte which had been received was the last. r/w = 0 write auxiliary memory. writing initiates the rx monitor channel. cr0/cr5 not used source register (src) when the bit cm of command register is at one, this register contains the data to be written in the control memory at the address indicated by the destination register. it rappresents the address of the data memory, or of one of the insert register, corresponding to the input data to be switched to the output indi- cated by the destination register. following you will find a detailed explanation case by case of the meaning of all the bits of this register. first case cm = 1 (bit of command register) command memory is selected. 7 0 pcm sr6 sr5 sr4 sr3 sr2 sr1 sr0 after reset 00 (h) pcm = 1 the source is pcm input. pcm = 0 the source is not pcm. the source is either multiplex inputs (gci) or insert registers. pcm = 1 pcm sr6 sr5 sr4 sr3 sr2 sr1 sr0 1 n1 n0 ts4 ts3 ts2 ts1 ts0 after reset 00 (h) if pcm is at 2 mb/s n0/1 pcm number : 0 to 3 ts0/4 time slot number : 0 to 31 if pcm is at 4 mb/s n1 pcm at 4 mb/s : 0 or 1 ts0/4 and n0 time slot number : 0 to 63 n0 = ts5 if pcm is at 8 mb/s ts0/4 and n0/1 time slot number : 0 to 127. n0 = ts5, n1 = ts6. pcm = 0 the source is multiplex input or insertion register. if n1 = 0 multiplexes are selected (gci or not) then n0 = 0 multiplex number : 0 STLC5460 23/54
n0 = 1 multiplex number : 1 ts0/4 time slot number : 0 to 31 if n1 = 1 insertion registers are selected. n0 = 0 and ts0/4 = 0. a insertion register 40 (h) is the source n0 = 1 and ts0/4 = 1. b insertion register 41(h) is the source . second case : cm = 0 (bit of command register) the auxiliary memory is selected. if channel is monitor channel (see destination register), the contents of source register are data : sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 m8 m7 m6 m5 m4 m3 m2 m1 it is proposed to initialise at ff, before starting normal operation using initialisation register t1 = 0 and t0 = 1. m8 will be transmitted first. if channel selected by destinationregister is command/indicate channels, the mean of bits of source register are : - for tx c/i with r/w = 0 write auxiliary memory. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 - - c6 c5 c4 c3 c2 c1 it is proposed to initialise at ff, before starting normal operation using initialisation register t1 = 0 and t0 = 1. c1/c6 primitive to transmit : c6 and c5 bits are taken into account depending on ci4m1 and ci4m0 bits of mconf register.c6 (or c4) will be transmitted first. - for tx c/i with r/w = 1 read auxiliary memory. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 pt1 pt0 c6 c5 c4 c3 c2 c1 pt 1/0 status of transmitting primitive. pt1 pt0 status 00 primitive has not been transmitted yet 01 primitive has been transmitted once 10 primitive has been transmitted twice 11 primitive has been transmitted more than twice. c6 to c1 primitive being transmitted. for rx c/i with r/w = 0, write auxiliary memory. this source register is not taken into account. for rx c/i with r/w = 1, read auxiliary memory. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 ovr pr c6 c5 c4 c3 c2 c1 STLC5460 24/54
ovr overrun. when ovr = 1, the previous primitive had not been read by the microprocessor; the current primitive has been put instead of the previous primitive. the previous primitive has been lost. pr primitive received. pr = 1, the current primitive has been received identical twice or more. c6 to c1 primitive received. destination register (dst) first case cm = 1 (bit of command register). command memory is selected. 7 0 pcm dt6 dt5 dt4 dt3 dt2 dt1 dt0 after reset 00 (h) pcm = 1 the destination is pcm output pcm = 0 the destination is not pcm. the destination is either multiplex (gci or not) or extract registers. pcm = 1 pcm dt6 dt5 dt4 dt3 dt2 dt1 dt0 1 n1 n0 ts4 ts3 ts2 ts1 ts0 pcm = 1 the destination is pcm output if pcm are at 2 mb/s: n0/1 pcm number: 0 to 3 ts0/4 time slot number 0 to 31. if pcm are at 4 mb/s n1 pcm at 4 mb/s: 0 or 1 ts0/4 and n0 time slot number 0 to 63 (n0 = ts5) if pcm is at 8 mb/s ts0/4 and n0/1 time slot number: 0 to 63 n0 = ts5, n1 = ts6. pcm = 0 the destination is multiplex output or extraxtion registers. if n1 = 0 multiplexes are selected (gci or not), then n0 = 0 multiplex number: 0 n0 = 1 multiplex number: 1 ts0/1 time slot number: 0 to 31 if n1 = 1 extraction registers are selected, then n0 = 0 and ts0/4 = 0 a extraction register 40 (h) is the destination n0 = 1 and ts0/4 = 1 b extraction register 41 (h) is the destination STLC5460 25/54
second case cm = 0 (bit of command register). the auxiliary memory is selected. pcm dt6 dt5 dt4 dt3 dt2 dt1 dt0 -montx - m0g2g1g0 pcm bit is not significant. the other bits are relevant only if multiplex is gci (see bits of multiplex con- figuration register : gci m0 and/or gci m1). mon command/indicate mon = 0. the channel is command/indicate mon = 1. the channel is mon channel. tx transmitter tx = 1. the transmit channel is selected. tx = 0. the receive channel is selected. m0 multiplex 0. m0 = 0. the gci multiplex 0 is selected. m0 = 1. the gci multiplex 1 is selected. g2/g0 gci 0/2 one of eight gci channels of the multiplex selected (one gci channel is constituted by five sub-channels : b1, b2, d, c/i and mon). if multiplex is not gci, the gci channels are not validated. the 32 time slots of the multiplex can be used for switching. status register (status) 7 0 bid busy prsr monr mont cir ext ins after reset 00 (h) each bit of this register is read only, except bid (bit) which can be written and read by the microproces- sor. bid bi-directional switching. bid = 1. two connection paths are established with the same m p instruction. the m p writes successively into three register: command register, source register and the destination register lastly, when the destination register has been written a write command memory starts to set up the connection required by the m p. the same information is used to establish a symmetrical connection: source register and destination register are swapped, and so are the ss0/1 and ds0/1 bit of command register. bid = 0: one connection path is established. the m p writes successively into three register: command register, source register and destination register lastly, when the destination register has been written a write command memory start to set up the connection required by the m p. STLC5460 26/54
busy busy. the memories cannot be accessed if this bit is at o1o. in this case, a new access of three memory access registers [command register (cmd); source register (src) and destination register (dst)] will be ignored. if the microprocessor has twait cycles (working with dtack or ready), the test busy is not necessary. prsr pseudo random sequence recovered. when the prs analyser is validated, prs bit is put to ooneo if the synchronization is performed. monr monitor channel receive. when this bit is at o1o, a byte has been received from one or more monitor channel. the microprocessor must read the receive monitor status register (rms) mont monitor channel transmit. when this bit is at o1o, one (or more) channel is transmitting a message and is ready to transmit a new byte of this message.the microprocessor must read the transmit monitor status register (tms). when this bit is at o0o, each channel is idle, and is ready to transmit a new message. cir command/indicate receive. when this bit is at o1o, a new primitive has been received from one or more command/indicate channel. the microprocessor can read the receive command/indicate status register (rcis). ext extract status. this bit is put ot o1o when a new byte has been written in the extract registers a or/ and b, when it is at o1o the extract registers can be read during 120 microseconds before changing. the bit is reset after the reading of the status register. ins insert status. when this bit is at o0o, the insert register a or/and b can be written during 120 m s before the next transmission. after the insert registers have been written the bit goes automatically to o1o, the bit is put at o0o after the reading of the status register. insertion a register (ins a) 7 0 ia7 ia6 ia5 ia4 ia3 ia2 ia1 ia0 after reset 00 (h) ia 0/7 this register contains the data to insert during the time slot (s) of the output multiplex(es) indicated by the command memory. after transferring ins, interrupt is generated insertion b register (ins b) 7 0 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 after reset 00 (h) ib 0/7 this register contains the data to insert during the time slot(s) of the output multiplex(es) indicated by the command memory. after transferring, ins interrupt is generated. STLC5460 27/54
extraction a register (ext a) 7 0 ea7 ea6 ea5 ea4 ea3 ea2 ea1 ea0 after reset 00 (h) ea 0/7 this register contains the data extracted during the time slot of input multiplex indicated by the command memory. after loading, ext interrupt is generated, in accordance with newe bit of comparison register extraction b register (ext b) 7 0 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 after reset 00 (h) eb 0/7 this register contains the data extracted during the time slot of input multiplex indicated by the command memory. after loading, ext interrupt is generated in accordance with newe bit of comparison register. interrupt register (int) 7 0 lsync pdif prs monr mont cir ext ins after reset 00 (h) lsync lost synchronisation. lsync = 0, pfs signal frequency is correct. lsyn = 1. pfs signal has not occurred when expected, or if double clock the number of clock pulses received is odd, or the data rate of one pcm received is not modulo 4 bits at 8 mb/s, or the data rate of one pcm received is not modulo 2 bits at 4 mb/s. pdif pcm different. pdif = 1. if one (or more) comparison (validated by the comparison register) between pcm is different. prs pseudo random sequence . when the prs analyser is validated (sav =1), prs bit is put to ooneo if the synchronisation is performed or lost (see prsr bit of status register). monr monitor channel receive. when this bit is at o1o, a byte has been received from the monitor channel defined by receive monitor status register (or an event) mont monitor channel transmit. when this bit is at o1o, the monitor channel (defined by transmit monitor status register) acknowledges the last command required by the microprocessor. cir command indicate receive. when this bit is at o1o, a new primitive has been received from the command/indicate channel defined by the receive command/indicate status register ext extract when this bit goes to o1o, the extract register a or/and b can be read during 120 microseconds before changing. ins insert when this bit goes to o1o, the content of insert register a or/and b has been transmitted. during 120 microseconds before the next transmission, the microprocessor can write a new word in accordance with tim (bit of cr register). STLC5460 28/54
mask register (mask) 7 0 mlsync mpdif mprs mmonr mmont mcir mext mins after reset ff (h) each interrupt of interrupt register can be masked by the mask bit associated if this last is at o1o. receive monitor status register (rmos) 7 0 event byte eom ab mo g2 g1 g0 after reset 00 (h) after reading, event bit goes to o0o. event event. event = 1. an event is occurred concerning the rx monitor channel identified by m0, g2, g1, g0. event = 0. no event occurred concerning the rx monitor channels. byte a new byte is available in auxiliary memory. the microprocessor can read this byte eom end of message. the previous byte which has been taken into account by the microprocessor was the last of the message. ab abort. abort = 1. the message received has been aborted by the transmitter. m0 gci multiplex 0 if mo = 0 gci multiplex 1 if mo = 1. g 0/2 gci channel 0 to 7 for each multiplex. transmit monitor status register (tmos) 7 0 event back to abt mo g2 g1 g0 after reset 00 (h) event event = 1. an event is occurred concerning the tx monitor channel identified by mo, g2, g1, g0. event = 0. no event concerning the tx monitor channels. back byte acknowledged. back = 1. the current byte transmitted has been acknowledged by the remote receiver. nb : when event = 1 and to = 0 and abt = 0 and back = 0, it means end of message. a newmessage can be transmitted. to time out. the remote receiver has not acknowledged the byte transmitted during 1millisecond (the timer is validated in accordance with timd of multiplexconfiguration 2 register). abt abort. the byte transmitting has been aborted. mo gci multiplex 0 if mo = 0 gci multiplex 1 if mo = 1. g 0/2 gci channel 0 to 7 for each multiplex. STLC5460 29/54
receive command/indicate status register (rcis) 7 0 event rrp ovr 0 mo g2 g1 g0 after reset 00 (h) event event = 1. a primitive has been received twice identically. the number of command/indicate channels is give by mo, g2, g1, g0. rrp read receive primitive rrp = 1 the mp has to read the primitive received in order to allow the next on to be processed. ovr overrun ovr = 1. the previous primitive has not been read by the microprocessor. mo if mo = 0, multiplex 0 if mo = 1, multiplex 1. g 0/2 gci 0 to gci 7 channel of each multiplex. test register (test) 7 0 fwd witg dca sav lp prsc dcg sgv after reset 00 (h) fwd false word detection fwd = 1, the counter indicates the number of wrong bytes fwd = 0, the counter indicates the number of wrong bits. witg word integrity. witg = 1. the first bit of the pseudo random sequence (2*11-1) is the firstbit of the channel (or subchannel) selected in the time slot at the beginning of the transmission. ` witg = 0. the first bit of the prs is transmitted without taking into accountthe place in the time slot. dca double channel for analyser. dca = 1. the analyser receives pseudo random sequence from two channels. dca = 0. the analyser receives pseudo random sequence from one channel. sav sequence analyser validation. when this bit goes to o1o, the analyser of pseudo random sequence (2*11-1) is connected instead of extract a register i f dca = 0, instead of extract a and extract b registers if dca = 1. then the synchronisation is researched. when sav = 0, the analyser is initiated. nb : when dca= 0, insert b register can be used normally. lp loopback. when lp = 1, the six data streams going out (pcm 0/3 and mux 0/1) are respectively connected instead of data stream coming from the 6 inputs (pcm 0/3 and mux 0/1). the loopback is transparent or not, depending on m0d,m1d, p0e, p1e, p2e, p3e bits of multiplex and pcm configuration registers. prsc pseudo random sequence corrupted. when this bit changes from 0 to 1, one prs bit is corrupted if dcg = 0, two prs bits are corrupted if dcg = 1 (one bit in each channel). after transmitting corrupted bit(s), prsc changes from o1o too 0o. dcg double channel for generator. dcg = 1. the generator transmits pseudo random sequence to two channels. dcg = 0. the generator transmits pseudo random sequence to one channel. sgv sequence generator validation. when this bit goes to o1o, the generator provides pseudo random binary sequence 2 * 11-1 in accordance with ccitt recommendation o.152. the generator is STLC5460 30/54
connected instead of insert a register if dcg = 0, and instead of insert a and insert b registers if dcg = 1. when sgv goes to o1o, the current contents of command register (cmd) is taken into account by the generator. in this case, command register means : 7 0 0 0 bch1 bch0 0 0 ach1 ach0 bch1/0 insert b channel 1/0. if generator transmits sequence instead of insert b register, the data rate for this channel is given by bch1/0 bch1 bch0 0 0 8 kb/s 0 1 16 kb/s 1 0 32 kb/s 1 1 64 kb/s ach1/0 insert a channel 1/0 if generator transmits sequence instead of insert a register, the data rate for this channel is given by ach1/0. ach1 ach0 0 0 8 kb/s 0 1 16 kb/s 1 0 32 kb/s 1 1 64 kb/s if dcg = 1, the data rate of prs generator is the sum of data rate insert b channel and insert a channel. if dcg = 0, the data rate of prs generator is equal to data rate of insert a channel. error counter register (ecr) 7 0 ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 after reset 00 (h). if the pseudo random sequence analyser is validated (sav = 1), this register indicates the number of errored bits received after the synchronisation of the pseudo random sequence. when error counter register indicates all o1os, the synchronisation is lost. after reading by the microprocessor, ecr is put to o0o. STLC5460 31/54
microprocessor interface timing tx parameter t min t max unit t1 set up time not chip select / ds/nrd 10 ns t2 set up time r/w / nwr / ds/nrd 10 ns t3 hold time not chip select / ds/nrd 0ns t4 hold time r/w / nwr / ds/nrd 0ns t5 width as/ale 20 ns t6 set up time address / as/ale 10 ns t7 hold time address / as/ale 10 ns t8 data valid after ds/nrd (rising edge) (30 pf) 40 ns t9 hold time data after ds/nrd (falling edge) 0ns t10 hold time data / ds/nrd 10 ns t11 set up time data / ds/nrd 10 ns t12 width ds/nrd 30 ns t13 nrdy/nwait delay ds/nrd 30 ns t14 nrdy/nwait delay / data 0ns t15 nrdy/nwait delay / ds/nrd nrdy/nwait delay / r/w / nwr 30 ns STLC5460 32/54
microprocessor interface timing multiplexed address/data microprocessor interface STLC5460 33/54
microprocessor interface timing non-multiplexed address/data microprocessor interface STLC5460 34/54
microprocessor interface timing variable cycle microprocessor interface STLC5460 35/54
del, ispp and pfsp bits of pcm configuration register are at zero (no delay)) 7 61 0 5 4 3 bit3 bit1 bit0 bit7 bit6 bit5 bit4 time slot 31 time slot 0 pfs txd0/3 tdm0/3 fsc delivered by the circuit t1 t5h t5l t3 t4 pdc ts0/3 t2 rxd0/3 t6 t7 t8 clock timing synchronization signals delivered by the system clocks received by the lcic tx parameter t min. t typ. t max. unit t1=1/f1 clock period if f1 = 16384khz clock period if f1 = 8192khz clock period if f1 = 4096khz 60 120 239 61 122 244 62 124 249 ns ns ns t2 bit-time if f1 = 16384khz bit-time if f1 = 8192khz bit-time if f1 = 4096khz 122 244 488 ns ns ns t3 set up time pfs/pdc 20 t1-20 ns t4 hold time pfs/pdc 20 12500-t1 ns t5 clock ratio t5h/t5l 75 100 125 % t6 pdc to data 50pf pdc to data 100pf 50 100 ns ns t7 set up time data/dcl 20 ns t8 hold time data/dcl 20 ns STLC5460 36/54
dcl delivered by din 0/1 fsc delivered by dout 0/1 bit0, time slot 0 the lcic the lcic bit7, time slot 31 t1 t5 t6 t7 t8 t2 pdc received by the lcic t3 t4 the four multiplex configuration registers are at zero (no delay between fsc and multiplexes) clock timing tdm synchronization clocks delivered by the lcic tx parameter t min. t typ. t max. unit t1 clock period if 4096khz clock period if 2048khz id pdc 244 488 id pdc ns ns t2 delay between pdc and dcl (30pf) 5 30 ns t3 delay between dcl and rising edge fsc (30pf) 30 ns t4 delay between dcl and falling edge fsc (30pf) 30 ns t5 duration fsc 488 ns t6 dcl to data 50pf dcl to data 100pf 50 100 ns ns t7 set up time data/dcl 20 ns t8 hold time data/dcl 20 ns STLC5460 37/54
dc specification absolute maximum ratings symbol parameter value unit v dd 5v power supply voltage -0.5 to 6.5 v input or output voltage -0.5, vdd +0.5 v t stg storage temperature -55, +125 c power dissipation symbol parameter test condition min. typ. max. unit p power consumption v dd = 5.25v 105 135 mw recommended dc operating conditions symbol parameter test condition min. typ. max. unit v dd 5v power supply voltage 4.75 5.25 mw t oper operating temperature -40 +85 c note 1: all the following specifications are valid only within these recommended operating conditions. ttl input dc electrical characteristics symbol parameter test condition min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v i il low level input current v i =0v 1 m a i ih high lvel input v i =v dd max -1 m a i ih_pullup high level input current for pullup vi = v dd max -50 m a c in input capacitance (see note 2) f = 1mhz @ 0v 2 4 pf c out output capacitance 4 pf c i/o bidir i/o capacitance 4 8 pf note 2: excluding package cmos output dc electrical characteristics symbol parameter test condition min. typ. max. unit v ol low level output voltage i ol = 4ma i ol = 2ma 0.5 0.4 v v oh high level output voltage i oh = 4ma i oh = 4ma v dd -0.5 v dd -0.4 v protection symbol parameter test condition min. typ. max. unit v esd electrostatic protection c = 100pf, r = 1.5k w 2000 v STLC5460 38/54
rcm subchannel select 01 and data rate 1 of 192 input timeslots 1 of 2 insert registers 1 of 192 output timeslots 1 of 2 extract registers cmd src dst command memory 194 words of 14 bits a in in 6 88 r=0 write cm=1 command memory appendix memory accesses command memory accesses. cm=1 write command memory: cmd and src registers are written if their bits have not the right value. cmd and src registers can be written in any order. dst register is always written the last read command memory in two steps: first step: register writing cmd register is written if its bits are not the right value. src register is not written. dst register is always written the last. r cm bits not used 1 1 register not writte n 1 of 192 output timeslots 1 of 2 extract register cmd src dst command memory 194 words of 14 bits a out out r cm selected channel 1 1 and data rate 1 of 192 input timeslots 1 of 2 insert registers 1 of 192 output timeslot s 1 of 2 extract register s cmd src dst 8 8 6 2 second step: register reading: cmd and src registers may be read in any order. dst register is not changed. STLC5460 39/54
auxiliary memory accesses: cm=0 write auxiliary memory: transmit command / indicate channels cmd and src registers are written if their bits have not the right value. cmd and src registers can be written in any order. dst register is always written the last. rcm bits not used 00 primitive to transmit mon tx 1 of 16 tx c/i 01 channels cmd src dst in auxiliary memory 16 words assigned to 8 tx c/i channels of mux0 & 8 tx c/i channels of mux1 a 4or6 6 r=0 write cm=0 auxiliary memory read auxiliary memory in two steps: transmit command / indicate channels first step: register writing: cmd register is written if its bits are not the right value. src register is not written. dst register is always written the last. rcm bits not used 1 0 register not writte n mon tx 1of16txc/i 01 channels cmd src dst rcm c/i channel status 10 channel status & primitive which has been transmitted mon tx 1of16txc/i 01 channels cmd src dst 6 4or6 2 2 auxiliary memory 16 words assigned to 8 tx c/i channels of mux0 & 8 tx c/i channels of mux1 out out a second step: register reading: cmd and src registers may be read in any order. dst register is not changed. STLC5460 40/54
auxiliary memory accesses: cm=0 write auxiliary memory: receive command / indicate channels cmd and src registers are written if their bits have not the right value. cmd and src registers can be written in any order. dst register is always written the last. rcm bits not used 00 primitive to initiate cmd src dst 4or6 6 i n auxiliary memory 16 words assigned to 8 rx c/i channels of mux0 & 8 rx c/i channels of mux1 a r=0 write cm=0 auxiliary memory mon tx 1 of 16 tx c/i 00 channels read auxiliary memory in two steps: receive command / indicate channels first step: register writing: cmd register is written if its bits are not the right value. src register is not written. dst register is always written the last. r c m bits not used 10 register not written cmd src dst rcm channel status 10 channel status & primitive which has been received mon tx 1 of 16 tx c/i 0 0 channels cmd src dst 6 4or6 2 a 2 auxiliary memory 16 words assigned to 8 rx c/i channels of mux0 & 8 rx c/i channels of mux1 out out mon tx 1of16txc/i 00 channels second step: register reading: cmd and src registers may be read in any order. dst register is not changed. STLC5460 41/54
auxiliary memory accesses: cm=0 write auxiliary memory: transmit monitor channels cmd and src registers are written if their bits have not the right value. cmd and src registers can be written in any order. dst register is always written the last. rcm command bits 00 data to transmit cmd src dst 8 6 3 in in auxiliary memory 16 words assigned to 8 tx mon channels of mux0 & 8 tx mon channels of mux1 a r=0 write cm=0 auxiliary memory mon tx 1 of 16 tx mon 11 channels read auxiliary memory in two steps: transmit monitor channels first step: register writing: cmd register is written if its bits are not the right value. src register is not written. dst register is always written the last. r c m bits not used 10 register not written cmd src dst r cm mon status 10 data which has been transmitted mon tx 1 of 16 tx mon 1 1 channels cmd src dst 6 8 2 5 a auxiliary memory 16 words assigned to 8 tx mon channels of mux0 & 8 tx mon channels of mux1 out out mon tx 1 of 16 tx mon 1 1 channels second step: register reading: cmd and src registers may be read in any order. dst register is not changed. STLC5460 42/54
auxiliary memory accesses: cm=0 write auxiliary memory: receive monitor channels cmd and src registers are written if their bits have not the right value. cmd and src registers can be written in any order. dst register is always written the last. rcm not used 00 data to initiate cmd src dst 8 6 in auxiliary memory 16 words assigned t o 8 rx mon channels of mux 0 & 8 rx mon channels of mux 1 a r=0 write cm=0 auxiliary memory mon tx 1of16txmon 10 channel s read auxiliary memory in two steps: receive monitor channels first step: register writing: cmd register is written if its bits are not the right value. src register is not written. dst register is always written the last. r cm bits not used 10 register not written cmd src dst rcm mon status 10 data which has been received mon tx 1 of 16 tx mon 1 0 channels cmd src dst 6 8 2 3 a auxiliary memory 16 words assigned to 8 rx mon channels of mux0 & 8 rx mon channels of mux1 out out mon tx 1of16txmon 10 channels second step, register reading: cmd and src registers may be read in any order. dst register is not changed. STLC5460 43/54
table 1: data memory address input source register pcm n1 n0 ts4 ts3 ts2 ts1 ts0 pcm 0 1 00 ts0tots31 pcm 1 01 ts0tots31 pcm 2 10 ts0tots31 pcm 3 11 ts0tots31 mux 0 0 0 0 ts 0 to ts 31 mux 1 1 ts 0 to ts 31 insert reg. a 1 000000 insert reg. b 000001 table 2: control memory address input destination register pcm n1 n0 ts4 ts3 ts2 ts1 ts0 pcm 0 1 00 ts0tots31 pcm 1 01 ts0tots31 pcm 2 10 ts0tots31 pcm 3 11 ts0tots31 mux 0 0 0 0 ts 0 to ts 31 mux 1 1 ts 0 to ts 31 extract reg. a 1 000000 extract reg. b 000001 STLC5460 44/54
table 3: auxiliary memory addresss mux channel destination register - mon tx - m0 g2 g1 g0 mux 0 ci rx - 00 0 gci channel 0 to 7 tx 0 1 gci channel 0 to 7 mon rx 1 0 gci channel 0 to 7 tx 1 1 gci channel 0 to 7 mux 1 ci rx 0 0 1 gci channel 0 to 7 tx 0 1 gci channel 0 to 7 mon rx 1 0 gci channel 0 to 7 tx 1 1 gci channel 0 to 7 table 4: auxiliary memory data channel source register tx command indicate - - c6 c5 c4 c3 c2 c1 rx command indicate ovr pr c6 c5 c4 c3 c2 c1 tx and rx monitor m8 m7 m6 m5 m4 m3 m2 m1 c1/6: primitive pr: primitive received ovr: overrun m1/8: byte STLC5460 45/54
write memory read status register busy read status register write command register w ith r /w=0 write source register write destination register end read status register busy read status register write command register w it h r/w=1 write destination register busy read command register (optional) read source register end ye s no ye s no ye s no read memory read status register read status register read destination register (optional) figure 4: control or auxiliary memory accesses memory access algorithm STLC5460 46/54
ex 1: source register 1 1 0 0 0 0 1 1 pcm 2 ts 3 destination register 0 0 1 0 1 1 0 1 mux 1 ts 13 (or mux 1 b2 of gci 3) the output mux 1-ts 13 receives the contents of the input pcm 2-ts 3 simple switching (bid=0) bidirectional switching (bid=1) the output mux 1-ts 13 receives the contents of the input pcm2-ts 3 and the output pcm 2-ts 3 receives the contents of the input mux 1-ts 13 ex 2: source register 0 1 0 0 0 0 0 0 insert register a destination register 0 0 101101 mux 1 ts 13 (or mux 1 b2 of gci 3) the output mux 1-ts 13 receives the contents of the insert register a simple switching (bid=0) bidirectional switching (bid=1) and the extract register a receives the contents of the input mux 1-ts 13 the output mux 1-ts 13 receives the contents of the insert register a figure 5: bidirectional switching channels at 64kbit/s STLC5460 47/54
ex 3: source register 0 1 0 0 0 0 0 0 insert register a destination register 0 1 0 0 0 0 0 1 the extract register b receives the contents of the insert register a simple switching (bid=0) bidirectional switching (bid=1) and the extract register a receives the contents of the insert register b extract register b the extract register b receives the contents of the insert register a ex 4: source register 1 0 1 1 0 1 0 1 pcm 1 ts 21 destination register 10100111 pcm 1 ts 7 the output pcm 1-ts 7 receives the contents of the input pcm 1-ts 21 simple switching (bid=0) bidirectional switching (bid=1) the output pcm 1-ts 7 receives the contents of the input pcm 1-ts21 and the output pcm 1-ts 21receives the contents of the input pcm 1-ts 7 this is a loopback two loopbacks are established figure 6: bidirectional switching and loopback STLC5460 48/54
ex 5:pcm to mux 10100010 pcm 1 ts 2 destination register 0 0 1 0 1 1 0 1 mux 1 ts 13 (or mux 1 b2 of gci 3) broadcast and the output mux 0-ts 25 receives the contents of the input pcm 1-ts 2 source register destination register 0 0 0 1 1 0 0 1 mux 0 ts 25 (or mux 0 b2 of gci 6) the output mux 1-ts 13 receives the contents of the input pcm 1-ts 2 and so on source register 01000000 insert register a destination register 0 0 0 1 1 1 0 0 mux 0 ts 28 (or mux 0 b1 of gci 7) and the output mux 1-ts 21 receives the contents of the insert register a the output mux 0-ts 28 receives the contents of the insert register a broadcast destination register 00110101 mux 1 ts 21 (or mux 1 b2 of gci 5) ex 6:insert register a to mux one source to several destinations figure 7: switching & broadcast STLC5460 49/54
ex7: channel at 16 kbit/s 11000011 pcm 2 ts 3 destination register 00101101 mux 1 ts 13 (or mux 1 b2 of gci 3) source register command register 01011001 rcm ch ss ds the output mux 1-ts 13 (bits 4-5) receives the contents of the input pcm 2-ts 3 (bits 2-3) simple switching (bid=0) bidirectional switching (bid=1) the output mux 1-ts 13 (bits 4-5) receives the contents of the input pcm 2-ts 3 (bits 2-3) ex8: channel at 16 kbit/s (insert register) the output pcm 2-ts 3 (bits 2-3) receives the contents of the input mux 1-ts 13 (bits 4-5) and source register 01000000 insert register a destination register 00101101 mux 1 ts 13 (or mux 1 b2 of gci 3) command register 01010001 rcm ch ss ds the output mux 1-ts 13 (bits 4-5) receives the contents of the insert register a bits 6-7. simple switching (bid=0) bidirectional switching (bid=1) the output mux 1-ts 13 (bits 4-5) receives the contents of the insert register a bits 6-7 and the extract register a (bits 6-7) receives the contents of the input mux 1-ts 13 (bits 4-5). r read; cm command memory; ch channel; ss source subchannel; ds destination subchannel figure 8: bidirectional switching channels at 16kbit/s STLC5460 50/54
ex 9: channels at 32 kbit/s 11110011 pcm 3 ts 19 destination register 00111101 mux 1 ts 29 (or mux 1 b2 of gci 7) source register command register 01 10010 0 rcmch ss ds the output mux 1-ts and 13 (bits4 to 7) receives the contents of the insert register a (bits 4 to 7). simple switching (bid=0) bidirectional switching (bid=1) the output mux 1-ts 13 (bits 4 to 7) receives the contents of the insert register a bits (4 to 7) the extract register a bits (4 to 7) receives the contents of the input mux 1-ts 13 bits (4 to7). r rea d; cm comma n d memory; ch ch an nel; ss s ource su bcha n nel; ds destina tion su bch a n n el simple switching (bid=0) bidirectional switching (bid=1) the output mux 1-ts 29 (bits 4 to 7) receives the contents of the input pcm 3-ts19 (bits 0 to 3) the output mux 1-ts 29 (bits 4 to 7) receives the contents of the input pcm 3-ts19 (bits 0 to 3) and the output pcm 3-ts19 (bits 0 to 3) receives the contents of the input mux 1-ts 29 (bits 4 to 7) source register 01000000 insert register a destination register 0 0101101 mux 1 ts 13 (or mux 1 b2 of gci 3) command register 0 110000 0 rcmch ss ds ex: 10: channels at 32 kbit/s (insert register) and figure 9: bidirectional switching channels at 32kbit/s STLC5460 51/54
interrupt no read interrupt register read receive mon status register monr=1 to know the number of the channel w hich has generated the interrupt read auxiliary memory with rx mon channel number into destination register the byte received is into source register end ye s and the status bits associated. byte=1 no ye s figure 10: interrupt generated by rx monitor channel. interrupt example STLC5460 52/54
plcc44 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 STLC5460 53/54
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics printed in italy all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STLC5460 54/54

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